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    SubjectRe: [LKML] Re: [PATCH v3] ad7877: keep dma rx buffers in seperate cache lines
    On Wed, May 12, 2010 at 08:35, Marc Gauthier wrote:
    > Mike Frysinger wrote:
    >> On Tue, May 11, 2010 at 23:23, FUJITA Tomonori wrote:
    >>> Seems that kmalloc is not cacheline aligned on some architectures but
    >>> they works. Probably, we might be just lucky because in general they
    >>> allocate larger buffers than 64 for DMA via kmalloc and the buffers
    >>> are aligned on the size?
    >> i think the magic combo is:
    >>  - DMA buffer is written to (receive)
    > [...]
    >>  - only on arches that need software cache coherency
    > In particular, when the architecture port uses cache invalidates that
    > throw away dirty lines.  They're equivalent to writing old data to a
    > cache line, so an unrelated kmalloc allocation in the same cache line
    > gets corrupted.

    true; i was thinking of the Blackfin implementation that only has a
    FLUSH+INV insn (i complain about the lack of a pure INV insn every now
    and again)
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      Last update: 2010-05-12 16:39    [W:4.029 / U:28.824 seconds]
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