Messages in this thread | | | Subject | Re: [PATCH v2] [RESEND] Handle instruction cache maintenance fault properly | From | Catalin Marinas <> | Date | Wed, 12 May 2010 12:01:27 +0100 |
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On Tue, 2010-05-11 at 11:33 +0100, Kirill A. Shutemov wrote: > Between "clean D line..." and "invalidate I line" operations in > v7_coherent_user_range(), the memory page may get swapped out. > And the fault on "invalidate I line" could not be properly handled > causing the oops. > > In ARMv6 "external abort on linefetch" replaced by "instruction cache > maintenance fault". Let's handle it as translation fault. It fixes the > issue. > > I'm not sure if it's reasonable to check arch version in run-time. > Let's do it in compile time for now. > > Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com> > Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
FWIW:
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
-- Catalin
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