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SubjectRe: [PATCH v3] ad7877: keep dma rx buffers in seperate cache lines
On Tue, 11 May 2010 02:11:41 -0400 Mike Frysinger <vapier.adi@gmail.com> wrote:

> > __ __ __ __unsigned __ __ __ __ __ __ __ __pending:1; __ __ __/* P: lock */
> > +
> > + __ __ __ /*
> > + __ __ __ __* DMA (thus cache coherency maintenance) requires the
> > + __ __ __ __* transfer buffers to live in their own cache lines.
> > + __ __ __ __*/
> > + __ __ __ u16 conversion_data[AD7877_NR_SENSE] ____cacheline_aligned;
> > __};

(^^stupid gmail)

> i'm not sure this is correct. the cached_aligned attribute makes sure
> it starts on a cache boundary, but it doesnt make sure it pads out to
> one. so it might work more of the time, but i dont think it's
> guaranteed.

yup. You'd need to put something like

int pad ____cacheline_aligned;
_after_ the trashable field.

Then look at the .s file and make sure it came out right ;)


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