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Subject[71/98] r8169: use correct barrier between cacheable and non-cacheable memory
2.6.32-stable review patch.  If anyone has any objections, please let us know.

------------------
From: David Dillow <dave@thedillows.org>

commit 4c020a961a812ffae9846b917304cea504c3a733 upstream.

r8169 needs certain writes to be visible to other CPUs or the NIC before
touching the hardware, but was using smp_wmb() which is only required to
order cacheable memory access. Switch to wmb() which is required to
order both cacheable and non-cacheable memory.

Noticed by Catalin Marinas and Paul Mackerras.

Signed-off-by: David Dillow <dave@thedillows.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

---
drivers/net/r8169.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -4316,7 +4316,7 @@ static netdev_tx_t rtl8169_start_xmit(st

tp->cur_tx += frags + 1;

- smp_wmb();
+ wmb();

RTL_W8(TxPoll, NPQ); /* set polling bit */

@@ -4676,7 +4676,7 @@ static int rtl8169_poll(struct napi_stru
* until it does.
*/
tp->intr_mask = 0xffff;
- smp_wmb();
+ wmb();
RTL_W16(IntrMask, tp->intr_event);
}




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