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    Subject[197/197] MIPS: Sibyte: Fix M3 TLB exception handler workaround.
    2.6.32-stable review patch.  If anyone has any objections, please let us know.

    ------------------

    From: Ralf Baechle <ralf@linux-mips.org>

    commit 3d45285dd1ff4d4a1361b95e2d6508579a4402b5 upstream.

    The M3 workaround needs to cmpare the region and VPN2 fields only.

    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
    Cc: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

    ---
    arch/mips/mm/tlbex.c | 22 ++++++++++++++++------
    1 file changed, 16 insertions(+), 6 deletions(-)

    --- a/arch/mips/mm/tlbex.c
    +++ b/arch/mips/mm/tlbex.c
    @@ -725,10 +725,15 @@ static void __cpuinit build_r4000_tlb_re
    * create the plain linear handler
    */
    if (bcm1250_m3_war()) {
    - UASM_i_MFC0(&p, K0, C0_BADVADDR);
    - UASM_i_MFC0(&p, K1, C0_ENTRYHI);
    + unsigned int segbits = 44;
    +
    + uasm_i_dmfc0(&p, K0, C0_BADVADDR);
    + uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
    uasm_i_xor(&p, K0, K0, K1);
    - UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
    + uasm_i_dsrl32(&p, K1, K0, 62 - 32);
    + uasm_i_dsrl(&p, K0, K0, 12 + 1);
    + uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
    + uasm_i_or(&p, K0, K0, K1);
    uasm_il_bnez(&p, &r, K0, label_leave);
    /* No need for uasm_i_nop */
    }
    @@ -1242,10 +1247,15 @@ static void __cpuinit build_r4000_tlb_lo
    memset(relocs, 0, sizeof(relocs));

    if (bcm1250_m3_war()) {
    - UASM_i_MFC0(&p, K0, C0_BADVADDR);
    - UASM_i_MFC0(&p, K1, C0_ENTRYHI);
    + unsigned int segbits = 44;
    +
    + uasm_i_dmfc0(&p, K0, C0_BADVADDR);
    + uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
    uasm_i_xor(&p, K0, K0, K1);
    - UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
    + uasm_i_dsrl32(&p, K1, K0, 62 - 32);
    + uasm_i_dsrl(&p, K0, K0, 12 + 1);
    + uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
    + uasm_i_or(&p, K0, K0, K1);
    uasm_il_bnez(&p, &r, K0, label_leave);
    /* No need for uasm_i_nop */
    }



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