Messages in this thread | | | Date | Wed, 21 Apr 2010 10:47:00 +0200 | From | Robert Richter <> | Subject | Re: [PATCH 11/12] perf, x86: implement AMD IBS event configuration |
| |
On 20.04.10 18:05:57, Robert Richter wrote: > > What is the problem with directly using the period here, rejecting > > any value that is off range or with bottom 4 bits set? > > Yes, I will create an updated version of this patch.
Stephane, do you think having the lower 4 bits set is worth an EINVAL? I would rather ignore them since the accuracy is not really necessary compared to a range lets say from 100000 cycles? Otherwise this will make the setup of ibs much more complicated. The check could be moved to userland and generate a waring or so.
-Robert
-- Advanced Micro Devices, Inc. Operating System Research Center email: robert.richter@amd.com
| |