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    SubjectRe: USB mass storage and ARM cache coherency
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    On Sun, 2010-03-07 at 09:07 +0530, James Bottomley wrote:
    > So, assuming full congruence of user space, can't you use the VMA as an
    > indicator? i.e. if we have no user space mappings, we have to flush the
    > icache ... if we have one or more, the icache has been flushed and
    > placing the same page congruently in a different address space benefits
    > from that prior flush, so consequently there's no need to flush again?

    the VMA ? Or you mean struct page -> mapping ? That would work I suppose
    in the case where we want to flush the icache pages for all pages mapped
    into user space. But on processors that support per-page execute
    permission, we really only want to flush pages that are executed from
    (lazily). In that case, we do need a dedicated bit to keep track of
    whether a given page has been flushed already.

    > I also think we've established the relevant facts for the I/O thread
    > (that we only need to either flush the kernel D cache or mark it as to
    > be flushed later on PIO reads). We're now into deep technicalities of
    > how the mm system operates at the architecture level, so perhaps we
    > should move this to linux-arch?

    No objection though moving threads after the fact is a recipe for
    trouble :-)

    Cheers,
    Ben.




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