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SubjectRE: [PATCH] serial: Add OMAP high-speed UART driver.


> -----Original Message-----
> From: Shilimkar, Santosh
> Sent: Tuesday, March 02, 2010 8:43 PM
> To: G, Manjunath Kondaiah; S, Venkatraman; Tony Lindgren;
> Raja, Govindraj; Greg KH; linux-serial@vger.kernel.org;
> linux-omap@vger.kernel.org; linux-kernel@vger.kernel.org;
> Kevin Hilman; Olof Johansson
> Subject: RE: [PATCH] serial: Add OMAP high-speed UART driver.
>
> > -----Original Message-----
> > From: G, Manjunath Kondaiah
> > Sent: Tuesday, March 02, 2010 8:34 PM
> > To: Shilimkar, Santosh; S, Venkatraman; Tony Lindgren;
> Raja, Govindraj; Greg KH; linux-
> > serial@vger.kernel.org; linux-omap@vger.kernel.org;
> linux-kernel@vger.kernel.org; Kevin Hilman; Olof
> > Johansson
> > Subject: RE: [PATCH] serial: Add OMAP high-speed UART driver.
> >
> >
> > Santosh,
> >
> > > -----Original Message-----
> > > From: Shilimkar, Santosh
> > > Sent: Tuesday, March 02, 2010 7:34 PM
> > > To: G, Manjunath Kondaiah; S, Venkatraman; Tony Lindgren;
> > > Raja, Govindraj; Greg KH; linux-serial@vger.kernel.org;
> > > linux-omap@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > Kevin Hilman; Olof Johansson
> > > Subject: RE: [PATCH] serial: Add OMAP high-speed UART driver.
> > >
> > > <snip snip>
> > > > > > --
> > > > > CDAC is a shadow register used for monitoring the DMA channel.
> > > > > I think it would be a lot
> > > > > simpler if omap_start_dma() always resets CDAC to 0, and the
> > > > > UART driver
> > > > > just not set it explicitly.
> > > >
> > > > This seems to be better option than exposing CDAC read/write API
> > > > to other drivers since user need to write '0' before
> > > starting any DMA
> > > > transfer which can be be done in omap_start_dma().
> > > >
> > > > I am wondering how other drivers are using DMA transfer
> > > API's without
> > > > resetting CDAC to zero.
> > > >
> > > It's needed only if some one is interested in that count.
> > > UART seems to
> > > using this counter where as other driver don't.
> > >
> > > Why do you think drivers need to know about counter value ?
> >
> > Reading of non zero value(after reset to zero and enabling
> dma channel)
> > from CDAC register indicates that, DMA transfer has started
> and user can
> > rely on DMA4_CCENi and DMA4_CCFNi element and frame counters.
> >
> > If the CDAC value is zero even after starting DMA channel, indicates
> > error.
> Not necessary. The DMA can still wait for the hw sync signal
> and the CDAC
> can remain 0 if the hw sync in not received. This will be any
> way returned
> by DMA error ( SYNC lost)
>
> This register was mainly suppose to be used for debug purposes.

As per TRM, CDAC can also be used for monitoring synchroized data
transfer apart from hw sync signal monitoring.

Anyway, we have are aligned to set this register to zero in
omap_start_dma() which will over ride this patch.

Regards,
Manjunath


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