Messages in this thread | | | Subject | Re: [RFC perf,x86] P4 PMU early draft | From | Peter Zijlstra <> | Date | Tue, 09 Feb 2010 09:54:31 +0100 |
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On Tue, 2010-02-09 at 15:23 +1100, Paul Mackerras wrote: > On Mon, Feb 08, 2010 at 09:45:04PM +0300, Cyrill Gorcunov wrote: > > > The main problem in implementing P4 PMU is that it has much more > > restrictions for event to MSR mapping. So to fit into current > > perf_events model I made the following: > > Is there somewhere accessible on the web where I can read about the P4 > PMU? I'm interested to see if the constraint representation and > search I used on the POWER processors would be applicable.
Mostly:
http://www.intel.com/Assets/PDF/manual/253669.pdf
Section 30.8 PERFORMANCE MONITORING (PROCESSORS BASED ON INTEL NETBURST MICROARCHITECTURE)
Section 30.9 PERFORMANCE MONITORING AND INTEL HYPER- THREADING TECHNOLOGY IN PROCESSORS BASED ON INTEL NETBURST MICROARCHITECTURE
Section A.8 PENTIUM 4 AND INTEL XEON PROCESSOR PERFORMANCE-MONITORING EVENTS
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