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SubjectRe: [PATCH] perf_events: AMD event scheduling (v3)
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On Wed, 2010-02-10 at 14:04 +0100, Stephane Eranian wrote:

> > @@ -2268,7 +2268,7 @@ static inline int amd_is_nb_event(struct
> > u64 val = hwc->config & K7_EVNTSEL_EVENT_MASK;
> > /* event code : bits [35-32] | [7-0] */
> > val = (val >> 24) | (val & 0xff);
> > - return val >= 0x0e0;
> > + return val >= 0xe00;
> > }
> >
> I don't understand the change from 0xe0 to 0xe00.
> That's not the same thing at all.
> Event select is bits 0-7 + 32-35.

OK that appears to be my bad, because you extended K7_EVNTSEL_EVENT_MASK
with bit 35 I thought NB events all had bit 35 set.

But looking at the AMD docs it does indeed appear to start at 0xe0, and
there are no events with bit 35 set, only a few with bit 32.

I'll switch it back to 0xe0.



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