Messages in this thread | | | Subject | Re: [RFC PATCH] perf: Add load latency monitoring on Intel Nehalem/Westmere | From | Peter Zijlstra <> | Date | Thu, 23 Dec 2010 11:11:24 +0100 |
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On Thu, 2010-12-23 at 16:28 +0800, Lin Ming wrote: > On Wed, 2010-12-22 at 18:45 +0800, Peter Zijlstra wrote: > > On Wed, 2010-12-22 at 11:08 +0100, Stephane Eranian wrote: > > > Yes, I think there is more to it than just data source, unfortunately. > > > If you want to avoid returning an opaque u64 (PERF_SAMPLE_EXTRA), then > > > you need to break it down: PERF_SAMPLE_DATA_SRC, PERF_SAMPLE_XX > > > and so on. > > > > I guess we can do things like: > > > > Satisfied by {L1, L2, L3, RAM}x{snoop, local, remote} + unknown, and > > encode "Pending core cache HIT" as L2-snoop or something, whatever is > > most appropriate. > > > > But does that cover every architecture? > > > > Also, since that doesn't require more that 4 bits to encode, we could > > try and categorize what else is around and try and create a well > > specified _EXTRA register, I mean, we still got 60bits left after this. > > Could you tell more about this well specified _EXTRA register?
Like how we should look at other archs (like POWER) and try and figure out what other useful information is available and come up with a generic format for that?
We could of course leave the 59 bits as reserved and fill it in later, and go with the data source bits only for now..
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