Messages in this thread | | | Subject | Re: edac_core: crashes on shutdown | From | Tobias Karnat <> | Date | Thu, 02 Dec 2010 23:34:14 +0100 |
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Am Donnerstag, den 02.12.2010, 19:37 +0100 schrieb Borislav Petkov: > On Thu, Dec 02, 2010 at 01:05:01PM -0500, Tobias Karnat wrote: > > Btw, are there any information available regarding the NMI option? > > > > parm: edac_op_state:EDAC Error Reporting state: 0=Poll,1=NMI (int) > > > > In edac.txt NMI is listed under FUTURE HARDWARE SCANNING. > > Well, looking at <arch/x86/kernel/traps.c:mem_parity_error()> this > should already work. But it is kinda of a hack, if I'm reading Doug > correctly: http://lkml.org/lkml/2010/9/21/144
This thread has many unknown abbreviations for me,
I thought as you wrote later, that this would be an option to use an interrupt instead of polling for edac in general.
But as far as I understand this, it is used for PCI bus errors?
And should be replaced for detection of PCI SERR and/or PCIE AER, are these the same as PCI bus errors?
> And yes, using some kind of an interrupt is much better than polling but > I don't know whether there's a single interrupt source for the error > types all edac drivers can decode and report. In the amd64_edac case, > we're piggybacking on MCE, for example. This was actually the initial > reason for 00740c58541b6087d78418cebca1fcb86dc6077d and dropping polling > from that driver.
From Intel Architectures Software Developer's Manual Part 3A:
"Starting with 45nm Intel 64 processor with CPUID signature DisplayFamily_DisplayModel encoding of 06H_1AH (...), the processor can report information on corrected machine-check errors and deliver a programmable interrupt for software to respond to MC errors, referred to as corrected machine-check error interrupt (CMCI)."
Seems to be unlikely for me on an Intel 975X Mainboard.
-Tobias
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