Messages in this thread Patch in this message | | | From | Jeff Ohlstein <> | Subject | [PATCH 13/20 v2] msm: 8x60: setup correct handlers for private interrupts | Date | Wed, 6 Oct 2010 00:42:52 -0700 |
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From: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Private Peripheral interrupts could be edge triggered or level triggered depending on the platform. Initialize handlers for these in board file.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> --- arch/arm/mach-msm/board-msm8x60.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index e7feb99..70087ca 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -44,7 +44,7 @@ static void __init msm8x60_init_irq(void) { unsigned int i; - gic_dist_init(0, MSM_QGIC_DIST_BASE, 1); + gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START); gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE; gic_cpu_init(0, MSM_QGIC_CPU_BASE); -- 1.7.2.1 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
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