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Subject[022/103] ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register
2.6.35-stable review patch.  If anyone has any objections, please let us know.


From: Catalin Marinas <>

commit 1a8e41cd672f894bbd74874eac601e6cedf838fb upstream.

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer

Cc: Nicolas Pitre <>
Signed-off-by: Catalin Marinas <>
Signed-off-by: Russell King <>
Signed-off-by: Greg Kroah-Hartman <>

arch/arm/mach-vexpress/ct-ca9x4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -225,7 +225,7 @@ static void ct_ca9x4_init(void)
int i;

- l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff);
+ l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00400000, 0xfe0fffff);

clkdev_add_table(lookups, ARRAY_SIZE(lookups));

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