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Subject[047/103] dmaengine: fix interrupt clearing for mv_xor
2.6.35-stable review patch.  If anyone has any objections, please let us know.


From: Simon Guinot <>

commit cc60f8878eab892c03d06b10f389232b9b66bd83 upstream.

When using simultaneously the two DMA channels on a same engine, some
transfers are never completed. For example, an endless lock can occur
while writing heavily on a RAID5 array (with async-tx offload support

Note that this issue can also be reproduced by using the DMA test

On a same engine, the interrupt cause register is shared between two
DMA channels. This patch make sure that the cause bit is only cleared
for the requested channel.

Signed-off-by: Simon Guinot <>
Tested-by: Luc Saillard <>
Acked-by: saeed bishara <>
Signed-off-by: Dan Williams <>
Signed-off-by: Greg Kroah-Hartman <>

drivers/dma/mv_xor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -162,7 +162,7 @@ static int mv_is_err_intr(u32 intr_cause

static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
- u32 val = (1 << (1 + (chan->idx * 16)));
+ u32 val = ~(1 << (chan->idx * 16));
dev_dbg(chan->device->, "%s, val 0x%08x\n", __func__, val);
__raw_writel(val, XOR_INTR_CAUSE(chan));

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