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SubjectRe: [PATCH resend 8/9] MIPS: Honor L2 bypass bit
On Sat, Oct 16, 2010 at 02:22:37PM -0700, Kevin Cernekee wrote:

> If CP0 CONFIG2 bit 12 (L2B) is set, the L2 cache is disabled and
> therefore Linux should not attempt to use it.
>
> Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
> ---
> arch/mips/mm/sc-mips.c | 5 +++++
> 1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
> index 5ab5fa8..d072b25 100644
> --- a/arch/mips/mm/sc-mips.c
> +++ b/arch/mips/mm/sc-mips.c
> @@ -79,6 +79,11 @@ static inline int __init mips_sc_probe(void)
> return 0;
>
> config2 = read_c0_config2();
> +
> + /* bypass bit */
> + if (config2 & (1 << 12))
> + return 0;

The spec I'm looking at says this bit is implementation defined so a
test for a particular CPU type would need to be added here.

Ralf


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