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    Subject[PATCH] perf_events: fix bogus AMD64 generic TLB events
    PERF_COUNT_HW_CACHE_DTLB:READ:MISS had a bogus umask value of 0 which
    counts nothing. Needed to be 0x7 (to count all possibilities).

    PERF_COUNT_HW_CACHE_ITLB:READ:MISS had a bogus umask value of 0 which
    counts nothing. Needed to be 0x3 (to count all possibilities).

    Signed-off-by: Stephane Eranian <eranian@google.com>

    ---

    diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
    index c2897b7..46d5844 100644
    --- a/arch/x86/kernel/cpu/perf_event_amd.c
    +++ b/arch/x86/kernel/cpu/perf_event_amd.c
    @@ -52,7 +52,7 @@ static __initconst const u64 amd_hw_cache_event_ids
    [ C(DTLB) ] = {
    [ C(OP_READ) ] = {
    [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
    - [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
    + [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
    },
    [ C(OP_WRITE) ] = {
    [ C(RESULT_ACCESS) ] = 0,
    @@ -66,7 +66,7 @@ static __initconst const u64 amd_hw_cache_event_ids
    [ C(ITLB) ] = {
    [ C(OP_READ) ] = {
    [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
    - [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
    + [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
    },
    [ C(OP_WRITE) ] = {
    [ C(RESULT_ACCESS) ] = -1,

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