Messages in this thread | | | Date | Mon, 11 Oct 2010 15:47:07 -0700 | From | "H. Peter Anvin" <> | Subject | Re: [RFC] [PATCH] allow low HZ values? |
| |
On 10/11/2010 03:33 PM, Thomas Gleixner wrote: > On Tue, 12 Oct 2010, Benjamin Herrenschmidt wrote: > >> On Mon, 2010-10-11 at 13:11 -0700, Tim Pepper wrote: >>> I'm not necessarily wanting to open up the age old question of "what is >>> a good HZ", but we were doing some testing on timer tick overheads for >>> HPC applications and this came up... >> >> Note that this is also very useful when working on CPU prototypes >> implemented in FPGAs and running at something like 12Mhz :-) > > /me hands benh 0.5$ for a FPGA upgrade
That's often not possible if the CPU cannot be mapped onto a single FPGA (either because the core is too large, multiple cores are tested, or because there is debugging logic is included.) The interconnects slows things down tremendously.
-hpa
| |