Messages in this thread | | | Date | Sun, 24 Jan 2010 05:52:01 +0000 (GMT) | From | "Maciej W. Rozycki" <> | Subject | Re: [patch 2/2] x86, irq: use 0x20 for the IRQ_MOVE_CLEANUP_VECTOR instead of 0x1f |
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On Wed, 13 Jan 2010, Suresh Siddha wrote:
> After talking to some more folks inside intel (Peter Anvin, Asit Mallick), > the safest option (for future compatibility etc) seen was to use vector 0x20 > for IRQ_MOVE_CLEANUP_VECTOR instead of using vector 0x1f (which is documented as > reserved vector in the Intel IA32 manuals). > > Also we don't need to reserve the entire privilege level (all 16 vectors in > the priority bucket that IRQ_MOVE_CLEANUP_VECTOR falls into), as the > x86 architecture (section 10.9.3 in SDM Vol3a) specifies that with in the > priority level, the higher the vector number the higher the priority. > And hence we don't need to reserve the complete priority level 0x20-0x2f for > the IRQ migration cleanup logic. > > So change the IRQ_MOVE_CLEANUP_VECTOR to 0x20 and allow 0x21-0x2f to be used > for device interrupts. 0x30-0x3f will be used for ISA interrupts (these > also can be migrated in the context of IOAPIC and hence need to be at a higher > priority level than IRQ_MOVE_CLEANUP_VECTOR).
I have troubles understanding what exactly this change is needed for (i.e. what's the difference between using vectors 0x20-0x2f and 0x30-0x3f as ExtINT interrupts, what's the gain from relocating them? -- they are transparent to the APIC, so the exact priority level used does not matter at all), but since I've been cc-ed, I have one question -- have you verified that with the new arrangement the mixed interrupt mode (where some interrupts come via the APIC and some via the 8259A PICs) still works?
Maciej
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