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    Subject[PATCH 18/52] drm/i915: Select the correct BPC for LVDS on Ironlake
    Date
    From: Zhao Yakui <yakui.zhao@intel.com>

    commit e5a95eb778690bc864eb330202d2c1b974caaeb4 upstream.

    Select the correct BPC for LVDS on Ironlake. If it is 18-bit LVDS panel,
    the BPC will be 6. When it is 24-bit LVDS panel, the BPC will 8.
    At the same time the BPC will be 8 when the output device is CRT/HDMI/DP.

    Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
    Signed-off-by: Eric Anholt <eric@anholt.net>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
    ---
    drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
    1 files changed, 12 insertions(+), 0 deletions(-)

    diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
    index d02016d..406b532 100644
    --- a/drivers/gpu/drm/i915/intel_display.c
    +++ b/drivers/gpu/drm/i915/intel_display.c
    @@ -2901,6 +2901,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,

    /* determine panel color depth */
    temp = I915_READ(pipeconf_reg);
    + temp &= ~PIPE_BPC_MASK;
    + if (is_lvds) {
    + int lvds_reg = I915_READ(PCH_LVDS);
    + /* the BPC will be 6 if it is 18-bit LVDS panel */
    + if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
    + temp |= PIPE_8BPC;
    + else
    + temp |= PIPE_6BPC;
    + } else
    + temp |= PIPE_8BPC;
    + I915_WRITE(pipeconf_reg, temp);
    + I915_READ(pipeconf_reg);

    switch (temp & PIPE_BPC_MASK) {
    case PIPE_8BPC:
    --
    1.6.6


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