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    SubjectRe: [tip:x86/asm] x86/i386: Make sure stack-protector segment base is cache aligned
    H. Peter Anvin wrote:
    > On 09/03/2009 08:47 PM, Tejun Heo wrote:
    >> H. Peter Anvin wrote:
    >>> On 09/03/2009 07:59 PM, Tejun Heo wrote:
    >>>> Another question. Other than saving and loading an extra segment
    >>>> register on kernel entry/exit, whether using the same or different
    >>>> segment registers doesn't look like would make difference
    >>>> performance-wise. If I'm interpreting the wording in the optimization
    >>>> manual correctly, it means that each non-zero segment based memory
    >>>> access will be costly regardless of which specific segment register is
    >>>> in use and there's no way we can merge segment based dereferences for
    >>>> stackprotector and percpu variables.
    >>> It's correct that it doesn't make any difference for access, only for load.
    >> Heh... here's a naive and hopeful plan. How about we beg gcc
    >> developers to allow different segment register and offset in newer gcc
    >> versions and then use the same one when building with the new gcc?
    >> This should solve the i386 problem too. It would be the best as we
    >> get to keep the separate segment register from the userland. Too
    >> hopeful?
    > I think it's possible to set the register in more recent gcc. Doing the
    > sane thing and having a symbol for an offset is probably worse.

    I was thinking about altering the build process so that we can use sed
    to substitute %gs:40 with %fs:40 while compiling. If it's already
    possible to override the register in more recent gcc, no need to go
    into that horror.

    > I can talk to H.J. Lu about this tomorrow.

    Great, please keep us posted.



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