Messages in this thread | | | Date | Tue, 22 Sep 2009 14:01:06 -0500 | Subject | TI PCIe-PCI bridge quirks | From | Gabe Black <> |
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Hi,
The TI XIO2000A/XIO2200A PCIe-PCI bridge (VID: 104C, DID: 8231) erroneously handles fast back-to-back transfers on its subordinate bus segment. The behavior is seen when there are multiple devices downstream and transfers from both devices result in a fast b2b transfer. This confuses the PCIe-PCI bridge and results in data corruption.
One way to work around the buggy bridge would be to disable fast b2b transfers on any device on the subordinate bus-segment by writing the appropriate bits in the device's pci-configspace command register.
Are there any suggestions on how this might be handled? Should this be addressed in the kernel?
Thanks, Gabe Black
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