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SubjectRe: [PATCH 0/2]: Get perf counters working on D-cache aliasing cpus.
From: Peter Zijlstra <>
Date: Fri, 18 Sep 2009 14:31:36 +0200

> Ingo just reminded me that we might want to do splice support for perf
> stuff. My plan was to have the splice thing allocate a new page, flip
> with a filled one from the buffer and send the filled one down to the
> splice consumer.
> Now having vmap'ed all that complicates stuff enourmously.
> Would it also work if we use order-1 pages on your platform instead of
> order-0, so that they are properly aligned for the d-cache?

You still have to make sure the order-1 page is order-1 virtually
aligned in userspace. But that would help only sparc64 because
SHMLBA happens to be 16K (2 * smallest supported PAGE_SIZE).

So, this won't handle sparc32 where the SHMLBA is 4MB.

MIPS has the same exact problems and has a large SHMLBA too.

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