Messages in this thread | | | From | "Sosnowski, Maciej" <> | Date | Mon, 14 Sep 2009 16:02:37 +0100 | Subject | RE: [PATCH 29/29] ioat2, 3: cacheline align software descriptor allocations |
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Williams, Dan J wrote: > All the necessary fields for handling an ioat2,3 ring entry can fit into > one cacheline. Move ->len prior to ->txd in struct ioat_ring_ent, and > move allocation of these entries to a hw-cache-aligned kmem cache to > reduce the number of cachelines dirtied for descriptor management. > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > ---
Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
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