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SubjectRe: kernel page table mapping for >1GB <3 GB for x86 arch without PAE
On Fri, 28 Aug 2009 12:44:25 -0700 (PDT)
joe Shmoe <jsmoe3@yahoo.com> wrote:

> No I am not talking about embedded systems. It is just an example.
> My question is what is preventing the kernel from setting up the page tables so that entire RAM can be mapped upto 4 GB.

The design of the x86 processor

You only have 4GB of virtual address space at any one time so you have to
fit the following within your 4GB virtual space

- Virtual addresses of the user space
- Mappings for physical memory
- Kernel virtual spaces (vmalloc etc)
- Various miscellaneous kernel mappings
- I/O MMIO space

Now you could in theory switch the page tables on kernel entry to get a
very big user space mapping and then instead of relying on the user space
being mapped you could map specific user pages or access them via their
physical address lookup.

That however means reloading %cr3 (page table base) which is very
expensive, and some very hard to implement locking on user space access.

Some other processor families have the notion of "spaces" or MMU
bypassing. The Sparc64 for example can access MMIO space without an MMU
mapping or virtual address being needed for it. x86 does not - it has
segments but the segments map into the 4GB space so they don't help here
hence the current implementation and 3G/1G split.


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