Messages in this thread Patch in this message | | | From | Borislav Petkov <> | Subject | [PATCH 10/14] amd64_edac: decode data cache MCEs | Date | Mon, 20 Jul 2009 18:13:01 +0200 |
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Those get reported in MC0_STATUS, see F10h BKDG (31116, rev. 3.28), Table 92 for more details.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> --- drivers/edac/amd64_edac.c | 56 +++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e4a0c91..ee13d59 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -2253,6 +2253,49 @@ static void amd64_decode_bus_error(struct mem_ctl_info *mci, edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR "Error Overflow"); } +static void amd64_decode_dc_mce(u64 mc0_status) +{ + u32 ec = mc0_status & 0xffff; + u32 xec = (mc0_status >> 16) & 0xf; + + pr_emerg(" Data Cache Error"); + + if (xec == 1 && TLB_ERROR(ec)) + pr_cont(": %s TLB multimatch.\n", LL(ec)); + else if (xec == 0) { + if (mc0_status & (1ULL << 40)) + pr_cont(" during Data Scrub.\n"); + else if (TLB_ERROR(ec)) + pr_cont(": %s TLB parity error.\n", LL(ec)); + else if (MEM_ERROR(ec)) { + u8 ll = ec & 0x3; + u8 tt = (ec >> 2) & 0x3; + u8 rrrr = (ec >> 4) & 0xf; + + /* see F10h BKDG (31116), Table 92. */ + if (ll == 0x1) { + if (tt != 0x1) + goto wrong_dc_mce; + + pr_cont(": Data/Tag %s error.\n", RRRR(ec)); + + } else if (ll == 0x2 && rrrr == 0x3) + pr_cont(" during L1 linefill from L2.\n"); + else + goto wrong_dc_mce; + } else if (BUS_ERROR(ec) && boot_cpu_data.x86 == 0xf) + pr_cont(" during system linefill.\n"); + else + goto wrong_dc_mce; + } else + goto wrong_dc_mce; + + return; + +wrong_dc_mce: + pr_warning("Corrupted DC MCE info?\n"); +} + void amd64_decode_nb_mce(struct mem_ctl_info *mci, struct err_regs *regs, int handle_errors, int ecc) { @@ -2345,16 +2388,25 @@ void decode_mce(struct mce *m) pr_cont("\n"); - amd64_decode_err_code(m->status & 0xffff); + switch (m->bank) { + case 0: + amd64_decode_dc_mce(m->status); + break; - if (m->bank == 4) { + case 4: regs.nbsl = (u32) m->status; regs.nbsh = (u32)(m->status >> 32); regs.nbeal = (u32) m->addr; regs.nbeah = (u32)(m->addr >> 32); amd64_decode_nb_mce(mci_lookup[0], ®s, 1, ecc); + break; + + default: + break; } + + amd64_decode_err_code(m->status & 0xffff); } /* -- 1.6.3.3
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