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SubjectRe: [PATCH] perf_counter: extensible perf_counter_attr
Corey Ashford writes:

> Ok, some disclosure here: we have not yet supported either of these features in
> the Power PMU's in any open source code (and perhaps the proprietary code too,
> but I don't know about that). Since these features are described in an IBM
> proprietary document, I can't describe how they work here, except to say that
> they are present in the chip.

Actually, the public PPC970FX user manual has a chapter on the
performance monitor unit which describes both thresholding and the
instruction matching CAM, among other things.

I think we can support thresholding using higher-order bits of the
event code when the low bits == PM_THRESH_TIMEO. We can only have one
PM_THRESH_TIMEO event on the PMU at any given time, so there can't be
any conflict over the thresholder settings.

The IMC is more problematic, but we can't do much with it on POWER5
and later processors anyway, due to various things being accessible
only in hypervisor mode, so I have been ignoring it. :)


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