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    SubjectRe: perf_counter Atom patch
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    On Tue, Jun 23, 2009 at 11:10 AM, Peter Zijlstra<a.p.zijlstra@chello.nl> wrote:
    > On Tue, 2009-06-23 at 16:34 +0800, Yong Wang wrote:
    >> > you could simply consider having 0 fixed counters and everything else would work
    >> > as expected. But there is a catch, unfortunately, in that there is erratum AE49
    >> > which says that there is only one enable bit to control the two generic counters
    >> > on Core Duo/Solo.
    >
    > Ah, that's similar to P6 like machines. The P6 docs say that to disable
    > a counter you should simply write all zeros (except the EN bit for ctr0)
    > to the control register (IIRC).
    >
    > I suppose we could do something similar on these errata cores, make
    > x86_pmu_disable_counter() write ARCH_PERFMON_EVENTSEL0_ENABLE instead.
    >
    > Would that work?
    >
    I suspect that to make this work correctly on P6 and Core Duo, you
    will have to enforce
    only one event/group to maintain the independence you expose at the
    user level. An
    Alternative would be to ensure that:
    - group leader in always in counter0
    - sibling events are created with disabled=0
    - ioctl(ENABLE/DISABLE) on siblings always fail

    Of course, this does not work, if the group leader event requires
    counter1. But I have to check
    if such restriction exists on Core Duo.


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