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    Subject[patch 26/58] drm/i915: allow tiled front buffers on 965+
    2.6.29-stable review patch.  If anyone has any objections, please let us know.

    ------------------

    From: Jesse Barnes <jbarnes@virtuousgeek.org>

    commit f544847fbaf099278343f875987a983f2b913134 upstream.

    This patch corrects a pretty big oversight in the KMS code for 965+
    chips. The current code is missing tiled surface register programming,
    so userland can allocate a tiled surface and use it for mode setting,
    resulting in corruption. This patch fixes that, allowing for tiled
    front buffers on 965+.

    Cc: stable@kernel.org
    Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
    Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
    Signed-off-by: Eric Anholt <eric@anholt.net>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

    ---
    drivers/gpu/drm/i915/i915_reg.h | 1 +
    drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
    2 files changed, 10 insertions(+)

    --- a/drivers/gpu/drm/i915/i915_reg.h
    +++ b/drivers/gpu/drm/i915/i915_reg.h
    @@ -1431,6 +1431,7 @@
    #define DISPPLANE_NO_LINE_DOUBLE 0
    #define DISPPLANE_STEREO_POLARITY_FIRST 0
    #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
    +#define DISPPLANE_TILED (1<<10)
    #define DSPAADDR 0x70184
    #define DSPASTRIDE 0x70188
    #define DSPAPOS 0x7018C /* reserved */
    --- a/drivers/gpu/drm/i915/intel_display.c
    +++ b/drivers/gpu/drm/i915/intel_display.c
    @@ -338,6 +338,7 @@ intel_pipe_set_base(struct drm_crtc *crt
    int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
    int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
    int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
    + int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
    int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
    u32 dspcntr, alignment;
    int ret;
    @@ -414,6 +415,13 @@ intel_pipe_set_base(struct drm_crtc *crt
    mutex_unlock(&dev->struct_mutex);
    return -EINVAL;
    }
    + if (IS_I965G(dev)) {
    + if (obj_priv->tiling_mode != I915_TILING_NONE)
    + dspcntr |= DISPPLANE_TILED;
    + else
    + dspcntr &= ~DISPPLANE_TILED;
    + }
    +
    I915_WRITE(dspcntr_reg, dspcntr);

    Start = obj_priv->gtt_offset;
    @@ -426,6 +434,7 @@ intel_pipe_set_base(struct drm_crtc *crt
    I915_READ(dspbase);
    I915_WRITE(dspsurf, Start);
    I915_READ(dspsurf);
    + I915_WRITE(dsptileoff, (y << 16) | x);
    } else {
    I915_WRITE(dspbase, Start + Offset);
    I915_READ(dspbase);



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