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Subject[PATCH 0/3] x86: adapt CPU topology detection for AMD Magny-Cours

Following patches add support for AMD Magny-Cours CPU.

I slightly change struct cpuinfo where I'd like to introduce
cpu_node_id to reflect CPU topology for AMD Magny-Cours CPU which
consists of two internal-nodes.

For all cores on the same multi-node CPU (Magny-Cours) /proc/cpuinfo
will show:
- same phys_proc_id
- cpu_node_id of the internal node (0 or 1)
- cpu_core_id (e.g. in range of 0 to 5)

I also change identification of core siblings (and thread siblings)
which will also be based on cpu_node_id in addition to phys_proc_id.

Furthermore I adapt the L3 cache information to reflect the cache
characteristics of one internal node instead of the entire package.

Primarily this changes are needed to correct core sibling information
for Magny-Cours. This CPU has two NBs on one physical package -- each
internal node has its own processor configuration space (i.e. set of
northbridge PCI functions).

Patches are against tip/master as of today.
Please consider patches 1 and 2 for .30.
Patch 3 should be applied to tip/x86/cpu where all the recent
cacheinfo changes reside (e.g. commit


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