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    SubjectRe: Who's responsible for configuring CLS on a cardbus device?
    Tejun Heo wrote:
    > Hello,
    > Robert Hancock wrote:
    >> Alan Cox wrote:
    >>> Currently its handled by pci_set_mwi() but there isn't actually a more
    >>> direct way to do this.
    > Thanks Alan.
    >> Yeah, I guess the assumption is that unless the device is using MWI it
    >> doesn't care about cache line size. However, in the case of the sata_sil
    >> controllers (and possibly other devices), the device cares about it for
    >> other purposes (I think it's FIFO handling in this case).
    >> Maybe we should just be setting the cache line size somewhere more
    >> basic, like pci_set_master or something?
    > Hmmm... given that it is something which is usually handled by the
    > system firmware, wouldn't it be more fitting to configure it from pci
    > hotplug code?

    I don't know cardbus devices at all, but Standard Hot-Plug Controller
    driver ('shpchp') and PCI Express Hot-Plug controller driver ('pciehp')
    configures cache line size of hot-added device. The cache line size is
    gotten from firmware through ACPI _HPP or _HPX method.

    Kenji Kaneshige

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      Last update: 2009-05-27 02:25    [W:0.046 / U:25.104 seconds]
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