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SubjectRe: [PATCH 0/29] x86/perfcounters: x86 and AMD cpu updates

* Robert Richter <robert.richter@amd.com> wrote:

> This patch series updates the perfcounters implementation mainly
> for the x86 architecture.

Wow, very nice series! Still havent looked through all of them, but
wanted to give some quick feedback that the splitup and direction
looks all good.

> Also, it introduces a data structure (struct pmu) describing a
> generic performance monitoring unit (pmu). This structure is a
> replacement for struct hw_perf_counter_ops. Similiar, I introduced
> struct x86_pmu for the x86 architecture (as a replacement for
> struct pmc_x86_ops).

Looks sensible. There will eventually be PMU features that dont fit
the hw-counter abstraction but which can still be expressed at the
general counter level.

> There are patches for x86 with some fixes and cleanups, a change
> in the model specific split and a complete rework of AMD pmu code.
> The result is simplified model specific code and more generalized
> and unified code. Features that are only supported by AMD or Intel
> are now implemented in vendor specific functions.

Nice!

> The AMD pmu differs to Intel, especially there is no status
> register and also there are no fixed counters. This makes a
> separate interrupt handler for AMD cpus necessary. Also, a global
> disable/enable of the performance counters (e.g. to avoid NMIs to
> protect the modification of a list) is expensive on AMD cpus
> leading to up to 4 msr reads/writes per counter. There is still
> some more work to do here to avoid this.

Yeah. The previous code was really just a first-level approximation
to show that it can be done.

> This patch series bases on the tip/percounters/core branch.
>
> I developed this patches based on 03ced43 and later rebased to
> 1b88991. The latest tip/percounters/core branch seems to be
> broken, no nmis are delivered, only perfcounter interrupts with no
> results on kerneltop. I am still debugging this. However, I could
> test successfully the patch series based on 03ced43 and want to
> release the patches anyway.

hm, it works all fine for me. This is "perf top" output from an
AMD/Barcelona box:

------------------------------------------------------------------------------
KernelTop: 139908 irqs/sec kernel: 9.5% [NMI, 100000 CPU cycles], (all, 16 CPUs)
------------------------------------------------------------------------------
events pcnt RIP kernel function
______ ______ _____ ________________ _______________
11038.00 - 22.2% - ffffffff8037a090 : clear_page_c
5842.00 - 11.7% - ffffffff804c6e02 : acpi_pm_read
2235.00 - 4.5% - ffffffff80579530 : page_fault
1518.00 - 3.0% - ffffffff8037a300 : copy_user_generic_string!
1184.00 - 2.4% - ffffffff80291598 : get_page_from_freelist
899.00 - 1.8% - ffffffff8057919a : _spin_lock
824.00 - 1.7% - ffffffff802a0c0a : unmap_vmas
739.00 - 1.5% - ffffffff8029d8a4 : __dec_zone_state
696.00 - 1.4% - ffffffff8028aafe : perf_swcounter_event
672.00 - 1.3% - ffffffff802a1b2e : handle_mm_fault
that's NMIs delivered to 16 cores. No lockups and no stuck IRQ
handling.

Would be nice to fix this...

Ingo


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