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    Subject[PATCH 4/6] x86: use native register access for native tlb flushing
    From: Chris Wright <chrisw@sous-sol.org>

    currently these are paravirtulaized, doesn't appear any callers rely on
    this (no pv_ops backends are using native_tlb and overriding cr3/4
    access).

    [ Impact: fix lockdep warning with paravirt and function tracer ]

    Signed-off-by: Chris Wright <chrisw@sous-sol.org>
    LKML-Reference: <20090423172138.GR3036@sequoia.sous-sol.org>
    Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
    ---
    arch/x86/include/asm/tlbflush.h | 8 ++++----
    1 files changed, 4 insertions(+), 4 deletions(-)

    diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
    index d3539f9..e2927c5 100644
    --- a/arch/x86/include/asm/tlbflush.h
    +++ b/arch/x86/include/asm/tlbflush.h
    @@ -17,7 +17,7 @@

    static inline void __native_flush_tlb(void)
    {
    - write_cr3(read_cr3());
    + native_write_cr3(native_read_cr3());
    }

    static inline void __native_flush_tlb_global(void)
    @@ -32,11 +32,11 @@ static inline void __native_flush_tlb_global(void)
    */
    raw_local_irq_save(flags);

    - cr4 = read_cr4();
    + cr4 = native_read_cr4();
    /* clear PGE */
    - write_cr4(cr4 & ~X86_CR4_PGE);
    + native_write_cr4(cr4 & ~X86_CR4_PGE);
    /* write old PGE again and flush TLBs */
    - write_cr4(cr4);
    + native_write_cr4(cr4);

    raw_local_irq_restore(flags);
    }
    --
    1.6.2.1
    --


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