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    Subject[PATCH] i2c: fix bit algorithm timeout for low values.
    Date
    From: Dave Airlie <airlied@redhat.com>

    When fetching DDC using i2c algo bit, we were often seeing timeouts
    before getting valid EDID on a retry. The VESA spec states 2ms is the
    DDC timeout, so when this translates into 1 jiffie and we are close
    to the end of the time period, it could return with a timeout less than
    2ms.

    Change this code to use time_after instead of time_after_eq.

    Signed-off-by: Dave Airlie <airlied@redhat.com>
    ---
    drivers/i2c/algos/i2c-algo-bit.c | 2 +-
    1 files changed, 1 insertions(+), 1 deletions(-)

    diff --git a/drivers/i2c/algos/i2c-algo-bit.c b/drivers/i2c/algos/i2c-algo-bit.c
    index d420cc5..e25e139 100644
    --- a/drivers/i2c/algos/i2c-algo-bit.c
    +++ b/drivers/i2c/algos/i2c-algo-bit.c
    @@ -104,7 +104,7 @@ static int sclhi(struct i2c_algo_bit_data *adap)
    * chips may hold it low ("clock stretching") while they
    * are processing data internally.
    */
    - if (time_after_eq(jiffies, start + adap->timeout))
    + if (time_after(jiffies, start + adap->timeout))
    return -ETIMEDOUT;
    cond_resched();
    }
    --
    1.6.0.6


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