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    SubjectRe: [PATCH 1/1] DaVinci: MMC: V4: MMC/SD controller driver for DaVinci family.
    On Friday 17 April 2009, Kumar, Purushotam wrote:
    > > I'm still not following the requirements here. Why would the hardware
    > > only need to have the FIFO primed for those two commands and not every
    > > kind of write?
    > This required by SD controller as suggested by IP designer. Please
    > look at SD controller spec at .
    > Please check section 3.2/3.6 and point no 11/10 in the controller spec.

    Those are in Chapter 3, "Procedures for Common Operations" ...
    that is, examples. Examples, as a rule, are there just to
    elaborate ("unpack") the more detailed text, not substitute
    for clear specification. (And TI is generally pretty good
    about providing sane documentation, thank you! Fewer problems
    than with "some" vendors.)

    In this case the spec says in a note in 2.7.2 that priming
    the fifo is needed for "write transactions" ... since no
    "fifo became empty" IRQ is generated. It does not limit it
    to the WRITE_BLOCK and WRITE_MULTIPLE_BLOCK commands.

    Those examples are for writing single and multiple blocks; there
    are no SDIO write operations shown, for example, or password
    passing operations. Those would also suffer from the lack of
    a "fifo became empty" IRQ.

    > It does not talk about priming by 32 bytes for any other command.

    Said diffferently, *every* PIO write transaction shown primes
    the fifo ... but there are no examples of non-block writes.

    > This restriction is from SD controller.

    Could you confirm that interpretation with the folk who have
    provided that silicon block?

    If your reading is correct, and it's really a restriction to
    those two commands, the documentation should change to say
    that "single and multiple block write commands" require FIFO
    priming ... not all "write transactions" as now written.

    - Dave

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