Messages in this thread Patch in this message | | | Date | Tue, 17 Mar 2009 16:17:48 +0000 | From | "Jan Beulich" <> | Subject | [PATCH] pci: Fix the definition of PCI_PM_CTRL_NO_SOFT_RESET |
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From: Dexuan Cui <dexuan.cui@intel.com>
As per PCI Bus Power Management Interface Specification Revision 1.2 this is bit 3, not bit 2, of the Power Management Control/Status register.
Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: stable <stable@kernel.org>
--- include/linux/pci_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
--- linux-2.6.29-rc8/include/linux/pci_regs.h 2009-03-17 17:14:16.000000000 +0100 +++ 2.6.29-rc8-pci-pm-ctrl-no-soft-reset/include/linux/pci_regs.h 2009-03-04 11:25:28.000000000 +0100 @@ -235,7 +235,7 @@ #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ -#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ +#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
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