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    SubjectRe: [RFC][PATCH 01/10] arm: mxc: New interrupt controller (TZIC) for i.MX5 family
    On Fri,  4 Dec 2009 04:47:01 +0200 Amit Kucheria wrote:

    > Freescale i.MX51 processor uses a different interrupt controller. Add the
    > driver and fix the Makefile to account for it.
    >
    > Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
    > ---
    > arch/arm/plat-mxc/Kconfig | 4 +
    > arch/arm/plat-mxc/Makefile | 9 ++-
    > arch/arm/plat-mxc/tzic.c | 180 ++++++++++++++++++++++++++++++++++++++++++++
    > 3 files changed, 192 insertions(+), 1 deletions(-)
    > create mode 100644 arch/arm/plat-mxc/tzic.c
    >
    > diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
    > new file mode 100644
    > index 0000000..3af8fc6
    > --- /dev/null
    > +++ b/arch/arm/plat-mxc/tzic.c
    > @@ -0,0 +1,180 @@
    > +/*
    > + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
    > + *
    > + * The code contained herein is licensed under the GNU General Public
    > + * License. You may obtain a copy of the GNU General Public License
    > + * Version 2 or later at the following locations:
    > + *
    > + * http://www.opensource.org/licenses/gpl-license.html
    > + * http://www.gnu.org/copyleft/gpl.html
    > + */
    > +
    ...
    > +
    > +/*!
    > + * Disable interrupt number "irq" in the TZIC
    > + *
    > + * @param irq interrupt source number
    > + */

    Hi,
    What processes these function comments (if anything does)?


    > +static void mxc_mask_irq(unsigned int irq)
    > +{
    > + int index, off;
    > +
    > + index = irq >> 5;
    > + off = irq & 0x1F;
    > + __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0 + (index << 2));
    > +}
    > +
    > +/*!
    > + * Enable interrupt number "irq" in the TZIC
    > + *
    > + * @param irq interrupt source number
    > + */
    > +static void mxc_unmask_irq(unsigned int irq)
    > +{
    > + int index, off;
    > +
    > + index = irq >> 5;
    > + off = irq & 0x1F;
    > + __raw_writel(1 << off, tzic_base + TZIC_ENSET0 + (index << 2));
    > +}
    > +
    > +static unsigned int wakeup_intr[4];
    > +
    > +/*
    > + * Set interrupt number "irq" in the TZIC as a wake-up source.
    > + *
    > + * @param irq interrupt source number
    > + * @param enable enable as wake-up if equal to non-zero
    > + * disble as wake-up if equal to zero
    > + *
    > + * @return This function returns 0 on success.
    > + */
    > +static int mxc_set_wake_irq(unsigned int irq, unsigned int enable)
    > +{
    > + unsigned int index, off;
    > +
    > + index = irq >> 5;
    > + off = irq & 0x1F;
    > +
    > + if (index > 3)
    > + return -1;
    > +
    > + if (enable)
    > + wakeup_intr[index] |= (1 << off);
    > + else
    > + wakeup_intr[index] &= ~(1 << off);
    > +
    > + return 0;
    > +}
    > +
    > +static struct irq_chip mxc_tzic_chip = {
    > + .name = "MXC_TZIC",
    > + .ack = mxc_mask_irq,
    > + .mask = mxc_mask_irq,
    > + .unmask = mxc_unmask_irq,
    > + .set_wake = mxc_set_wake_irq,
    > +};
    > +
    ...
    > +
    > +/*
    > + * enable wakeup interrupt
    > + *
    > + * @param is_idle 1 if called in idle loop (enset registers);
    > + * 0 to be used when called from low power entry
    > + * @return 0 if successful; non-zero otherwise
    > + *
    > + */
    > +int tzic_enable_wake(int is_idle)
    > +{
    > + unsigned int i, v;
    > +
    > + __raw_writel(1, tzic_base + TZIC_DSMINT);
    > + if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
    > + return -EAGAIN;
    > +
    > + if (likely(is_idle)) {
    > + for (i = 0; i < 4; i++) {
    > + v = __raw_readl(tzic_base + TZIC_ENSET0 + i * 4);
    > + __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4);
    > + }
    > + } else {
    > + for (i = 0; i < 4; i++) {
    > + v = wakeup_intr[i];
    > + __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4);
    > + }
    > + }
    > + return 0;
    > +}
    > --

    thanks,
    ---
    ~Randy


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