Messages in this thread | | | Subject | Re: [Fdutils] DMA cache consistency bug introduced in 2.6.28 | From | "Pallipadi, Venkatesh" <> | Date | Wed, 23 Dec 2009 13:34:28 -0800 |
| |
On Wed, 2009-12-23 at 12:34 -0800, alain wrote: > Pallipadi, Venkatesh wrote: > > MSI interrupt being delivered to CPU 0. I cannot think of any reason why > > this can break dma. We can probably try adding some dummy HPET read > > after dma write, to see if that flushes things properly. > > Shouldn't that be "... some dummy HPET read _before_ dma write...". In > order to ensure that DMA cache is consistent _before_ dma controller > reads it? >
Yes. I meant after the contents of the buffer is changed and before the DMA transfer and the controller reading it.
Thanks, Venki
| |