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SubjectRe: DMA cache consistency bug introduced in 2.6.28
Date
Linus Torvalds <torvalds@linux-foundation.org> writes:

> On x86, where all caches are supposed to be totally coherent (except for
> I$ under very special circumstances),

BTW SWIOTLB is a non-coherent "cache" in some sense, though I'd be
surprised if it's related. Anyway mentioning $CPU and $RAM at the very
least would be a good idea in such cases.
--
Krzysztof Halasa


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