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    SubjectRe: Irq architecture for multi-core network driver.
    From
    >>
    >> Does your hardware do flow-based queues?  In this model you have
    >> multiple rx queues and the hardware hashes incoming packets to a single
    >> queue based on the addresses, ports, etc. This ensures that all the
    >> packets of a single connection always get processed in the order they
    >> arrived at the net device.
    >>
    >
    > Indeed, this is exactly what we have.
    >
    >
    >> Typically in this model you have as many interrupts as queues
    >> (presumably 16 in your case).  Each queue is assigned an interrupt and
    >> that interrupt is affined to a single core.
    >

    > Certainly this is one mode of operation that should be supported, but I
    > would also like to be able to go for raw throughput and have as many cores
    > as possible reading from a single queue (like I currently have).
    >
    Well, you could let the NIC firmware(f/w) handle this. The f/w would
    know which interrupt was just injected recently.In other words it
    would have a history of which CPU's would be available. So if some
    previously interrupted CPU isn't making good progress then the
    firmware should route the incoming response packets to a different
    queue. This way some other CPU will pick it up.


    > David Daney
    > --
    Chetan Loke
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