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    SubjectRe: [BISECTED] drm: random hang since 620f378 "drm: prune modes when ..."
    On Mon, 14 Dec 2009 20:38:09 +0000
    Arnd Bergmann <> wrote:

    > On Monday 14 December 2009 18:20:15 Jesse Barnes wrote:
    > > You can disable most of that code by loading i915 with
    > > 'powersave=0'. If that patch really is at fault the powersave=0
    > > should work around the issue as well.
    > Ok, I'll try that and let you know. Running the kernel before your
    > patch has not crashed yet after two days of uptime. Now running
    > with your patch but nothing else. When that crashes, I'll try
    > the latest mainline with powersave=0.

    Ok great.

    > > It's been implicated in another issue (some display flicker and
    > > underruns) so I'm pretty sure there's something wrong with it in
    > > some configurations at least...
    > I haven't seen that yet. FWIW, the device in question is

    [snip 4 series pci info]

    > Let me know if you have a patch you want me to test.

    This patch removes the suspect portion of the dynamic clock control
    code. Hopefully it'll be as stable as powersave=0 in your config
    (assuming powersave=0 works :).

    Jesse Barnes, Intel Open Source Technology Center

    diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_d
    index 279dc96..b8730de 100644
    --- a/drivers/gpu/drm/i915/intel_display.c
    +++ b/drivers/gpu/drm/i915/intel_display.c
    @@ -3825,8 +3825,6 @@ void intel_decrease_renderclock(struct drm_device *dev)
    /* Down to minimum... */
    gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
    gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
    - pci_write_config_word(dev->pdev, GCFGC, gcfgc);
    } else if (IS_I965G(dev)) {
    u16 gcfgc;

     \ /
      Last update: 2009-12-14 21:53    [W:0.068 / U:4.412 seconds]
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