Messages in this thread | | | Date | Sun, 8 Nov 2009 14:30:59 -0800 | From | Arjan van de Ven <> | Subject | Re: [PATCH v2] cpuidle: Fix the menu governor to boost IO performance |
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On Sun, 8 Nov 2009 22:59:43 +0100 Corrado Zoccolo <czoccolo@gmail.com> wrote: > > > > the exit latency is +/- 1 us, the entry latency is similar, and then > > you're pretty close to 5 already (esp if you keep in mind that to > > break even on energy you also need to be in the C state for a > > little bit)... > > There are also performance considerations for using C1 (HLT). > Quoting from http://www.intel.com/Assets/PDF/manual/248966.pdf (8-19): > On processors supporting HT Technology, operating systems should use > the HLT instruction if one logical processor is active and the other > is not. HLT will allow an idle > logical processor to transition to a halted state; this allows the > active logical > processor to use all the hardware resources in the physical package.
I think we all agree that long term polling is bad ;-) (even though we use rep nop in the polling loop which is also a HT yield).
There's just the very short sleeps (where short is "single digit usecs") where the rules are slightly different.
> > this check is supposed to catch the known timer cases; those > > are rather accurate in prediction > > Unfortunately, I have seen polling residency times > 1ms, so it must > not be so accurate.
well the question is... is this a measurement error or an error in when polling is chosen. We obviously need to fix it whatever it is, but... first need to chase down really which it is.
-- Arjan van de Ven Intel Open Source Technology Centre For development, discussion and tips for power savings, visit http://www.lesswatts.org
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