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    Subject[PATCH 1/9] pci: separate pci_setup_bridge to small functions

    prepare to use those small functions according to resource type later

    Signed-off-by: Yinghai Lu <yinghai@kernel.org>

    ---
    drivers/pci/setup-bus.c | 54 +++++++++++++++++++++++++++++++++++++++---------
    1 file changed, 44 insertions(+), 10 deletions(-)

    Index: linux-2.6/drivers/pci/setup-bus.c
    ===================================================================
    --- linux-2.6.orig/drivers/pci/setup-bus.c
    +++ linux-2.6/drivers/pci/setup-bus.c
    @@ -134,19 +134,12 @@ EXPORT_SYMBOL(pci_setup_cardbus);
    config space writes, so it's quite possible that an I/O window of
    the bridge will have some undesirable address (e.g. 0) after the
    first write. Ditto 64-bit prefetchable MMIO. */
    -static void pci_setup_bridge(struct pci_bus *bus)
    +static void pci_setup_bridge_io(struct pci_bus *bus)
    {
    struct pci_dev *bridge = bus->self;
    struct resource *res;
    struct pci_bus_region region;
    - u32 l, bu, lu, io_upper16;
    - int pref_mem64;
    -
    - if (pci_is_enabled(bridge))
    - return;
    -
    - dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
    - bus->secondary, bus->subordinate);
    + u32 l, io_upper16;

    /* Set up the top and bottom of the PCI I/O segment for this bus. */
    res = bus->resource[0];
    @@ -172,7 +165,13 @@ static void pci_setup_bridge(struct pci_
    pci_write_config_dword(bridge, PCI_IO_BASE, l);
    /* Update upper 16 bits of I/O base/limit. */
    pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
    -
    +}
    +static void pci_setup_bridge_mmio(struct pci_bus *bus)
    +{
    + struct pci_dev *bridge = bus->self;
    + struct resource *res;
    + struct pci_bus_region region;
    + u32 l;
    /* Set up the top and bottom of the PCI Memory segment
    for this bus. */
    res = bus->resource[1];
    @@ -187,6 +186,14 @@ static void pci_setup_bridge(struct pci_
    dev_info(&bridge->dev, " bridge window [mem disabled]\n");
    }
    pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
    +}
    +static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
    +{
    + struct pci_dev *bridge = bus->self;
    + struct resource *res;
    + struct pci_bus_region region;
    + u32 l, bu, lu;
    + int pref_mem64;

    /* Clear out the upper 32 bits of PREF limit.
    If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
    @@ -219,10 +226,37 @@ static void pci_setup_bridge(struct pci_
    pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
    pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
    }
    +}
    +static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
    +{
    + struct pci_dev *bridge = bus->self;
    +
    + if (pci_is_enabled(bridge))
    + return;
    +
    + dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
    + bus->secondary, bus->subordinate);
    +
    + if (type & IORESOURCE_IO)
    + pci_setup_bridge_io(bus);
    +
    + if (type & IORESOURCE_MEM)
    + pci_setup_bridge_mmio(bus);
    +
    + if (type & IORESOURCE_PREFETCH)
    + pci_setup_bridge_mmio_pref(bus);

    pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
    }

    +static void pci_setup_bridge(struct pci_bus *bus)
    +{
    + unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
    + IORESOURCE_PREFETCH;
    +
    + __pci_setup_bridge(bus, type);
    +}
    +
    /* Check whether the bridge supports optional I/O and
    prefetchable memory ranges. If not, the respective
    base/limit registers must be read-only and read as 0. */


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