lkml.org 
[lkml]   [2009]   [Nov]   [12]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
Date
From
SubjectRe: [PATCH] x86_64: Limit the number of processor bootup messages
On Mon, Nov 02, 2009 at 11:21:39AM -0800, Mike Travis wrote:

> >> [ 90.981402] CPU: L1 I cache: 32K, L1 D cache: 32K
> >> [ 90.985888] CPU: L2 cache: 256K
> >> [ 90.988032] CPU: L3 cache: 24576K
> >
> > I would recommend to drop the cache information; this can be easily
> > gotten at runtime and is often implied in the CPU name anyways
> > (and especially L1 and increasingly L2 too change only very rarely)
>
> Ok, though because of future system upgrades to a UV system, you can
> end up with slightly different processors (of the same family). The
> only differences I've detected so far in testing is the stepping has
> changed.

I happened to be annoyed by dozens of these three printk's earlier,
and hacked up the following (currently untested) patch.

But I don't disagree with Andi either, that it's not particularly useful,
and we can get all this from userspace in /proc/cpuinfo, or x86info.

If someone still finds it valuable to have the kernel keep printing it
though, perhaps something like the following ?

Dave



On processors with a large number of cores, we print dozens of lines of information about
the CPU cache topology, most of which is unnecessary.
This patch reduces spew a lot (down to a single line unless someone uses a mix of processors
with different cache sizes)

- Check if the total cache size on APs is equal to the boot processors cache size.
Print nothing if equal.
- The three printk's will fit on one line.

Signed-off-by: Dave Jones <davej@redhat.com>

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 804c40e..cc4f44d 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -358,9 +362,9 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_HT
unsigned int cpu = c->cpu_index;
#endif
+ static int is_initialized;

if (c->cpuid_level > 3) {
- static int is_initialized;

if (is_initialized == 0) {
/* Init num_cache_leaves from boot CPU */
@@ -488,6 +492,21 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
#endif
}

+ c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
+
+ /*
+ * cache topology on all AP's is likely equal to that of the BP
+ * if this is the case, don't bother printing anything out for the AP's.
+ */
+ if (is_initialized != 0) {
+ if (c->x86_cache_size == boot_cpu_data.x86_cache_size)
+ return l2;
+ else
+ printk(KERN_INFO "CPU: AP has different cache size (%d) to BP (%d)\n",
+ c->x86_cache_size,
+ boot_cpu_data.x86_cache_size);
+ }
+
if (trace)
printk(KERN_INFO "CPU: Trace cache: %dK uops", trace);
else if (l1i)
@@ -495,16 +512,12 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)

if (l1d)
printk(KERN_CONT ", L1 D cache: %dK\n", l1d);
- else
- printk(KERN_CONT "\n");

if (l2)
- printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
+ printk(KERN_CONT ", L2 cache: %dK\n", l2);

if (l3)
- printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
-
- c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
+ printk(KERN_CONT ", L3 cache: %dK\n", l3);

return l2;
}

\
 
 \ /
  Last update: 2009-11-12 23:57    [W:0.112 / U:1.052 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site