Messages in this thread | | | Date | Thu, 29 Oct 2009 13:39:27 +0100 | Subject | Re: [PATCH 2/2] Add COH 901 318 DMA driver platform config for U300 v3 | From | Linus Walleij <> |
| |
2009/10/28 Dan Williams <dan.j.williams@intel.com>:
> On Wed, Oct 28, 2009 at 8:19 AM, Linus Walleij > <linus.walleij@stericsson.com> wrote: > [..] >> +#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \ >> + COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \ >> + COH901318_CX_CFG_LCR_DISABLE | \ >> + COH901318_CX_CFG_TC_IRQ_ENABLE | \ >> + COH901318_CX_CFG_BE_IRQ_ENABLE) >> +#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \ >> + COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ >> + COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ >> + COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ >> + COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ >> + COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ >> + COH901318_CX_CTRL_MASTER_MODE_M1RW | \ >> + COH901318_CX_CTRL_TCP_DISABLE | \ >> + COH901318_CX_CTRL_TC_IRQ_DISABLE | \ >> + COH901318_CX_CTRL_HSP_DISABLE | \ >> + COH901318_CX_CTRL_HSS_DISABLE | \ >> + COH901318_CX_CTRL_DDMA_LEGACY | \ >> + COH901318_CX_CTRL_PRDD_SOURCE) >> +#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \ >> + COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ >> + COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ >> + COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ >> + COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ >> + COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ >> + COH901318_CX_CTRL_MASTER_MODE_M1RW | \ >> + COH901318_CX_CTRL_TCP_DISABLE | \ >> + COH901318_CX_CTRL_TC_IRQ_DISABLE | \ >> + COH901318_CX_CTRL_HSP_DISABLE | \ >> + COH901318_CX_CTRL_HSS_DISABLE | \ >> + COH901318_CX_CTRL_DDMA_LEGACY | \ >> + COH901318_CX_CTRL_PRDD_SOURCE) >> +#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \ >> + COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ >> + COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ >> + COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ >> + COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ >> + COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ >> + COH901318_CX_CTRL_MASTER_MODE_M1RW | \ >> + COH901318_CX_CTRL_TCP_DISABLE | \ >> + COH901318_CX_CTRL_TC_IRQ_ENABLE | \ >> + COH901318_CX_CTRL_HSP_DISABLE | \ >> + COH901318_CX_CTRL_HSS_DISABLE | \ >> + COH901318_CX_CTRL_DDMA_LEGACY | \ >> + COH901318_CX_CTRL_PRDD_SOURCE) > > You go through the hassle of defining these flag combination sets... > >> + .param.config = COH901318_CX_CFG_CH_DISABLE | >> + COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY | >> + COH901318_CX_CFG_LCR_DISABLE | >> + COH901318_CX_CFG_TC_IRQ_ENABLE | >> + COH901318_CX_CFG_BE_IRQ_ENABLE, > > ...but then don't use them to cut down on the line count in the > definition of these parameters?
We do, look further below:
+ { + .number = U300_DMA_GENERAL_PURPOSE_0, + .name = "GENERAL 00", + .priority_high = 0, + + .param.config = flags_memcpy_config, + .param.ctrl_lli_chained = flags_memcpy_lli_chained, + .param.ctrl_lli = flags_memcpy_lli, + .param.ctrl_lli_last = flags_memcpy_lli_last, + },
Only the general purpose channels support memcpy and these are all set up the same way (for accelerating memcpy() operations).
The rest of the channels are, mem -> io, io -> mem, io -> io and the io (device DMA) configurations are individual and varies greatly with hardware. For some currently unused hardware we haven't even defined the proper flags yet, and e.g. changing the burst size of an individual channel without affecting the rest is something a developer is very likely to do.
Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |