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SubjectRe: Difference between atomic operations and memory barriers
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On Wed, 28 Oct 2009 12:00:05 +0200, Boaz Harrosh said:

> What don't you know? the CPU that started it all was like that, the x86 16-bit
> "large" and "huge" model had a double register seg:offset set, also in-memory
> was double-ints(2*16) even the i386 was running 16 bit modes for a long time.

Yes, but there were instructions to load segment registers, and those were
atomic, and there were instructions to compute effective addresses based on the
segment registers, and those were basically atomic. But you never had a chance
to see a partly loaded segment register (just like in today's virtual memory
equivalents, a PTE's effect is basically atomic - you never see half the
address bits of a PTE take effect and not the other half).

Yes, if a segment register wasn't set right, you'd load/store from the wrong
place in memory (we *still* have that, playing with %fs and %gs). But that's
different than an actual load or store only half-happening, or happening partly
to an old place and partly to a new one, because a segment register is only
half-finished laoding.

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