Messages in this thread Patch in this message | | | Date | Wed, 14 Oct 2009 20:51:31 -0400 | From | Dave Jones <> | Subject | Re: [X86] PCI: Use generic cacheline sizing instead of per-vendor tests. |
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On Wed, Oct 14, 2009 at 04:31:39PM -0400, Dave Jones wrote:
> I've been carrying a variant of this code in Fedora for a while, > that prints debug information. There are a number of cases where we > are currently setting the PCI cacheline size to 32 bytes, when the CPU > cacheline size is 64 bytes. With this patch, we set them both the same.
In case anyone is curious, here's the version we carried in Fedora for a while..
Dave
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 2202b62..f371fe8 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -432,6 +432,22 @@ int __init pcibios_init(void) else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL) pci_cache_line_size = 128 >> 2; /* P4 */ + if (c->x86_clflush_size != (pci_cache_line_size <<2)) + printk(KERN_DEBUG "PCI: old code would have set cacheline " + "size to %d bytes, but clflush_size = %d\n", + pci_cache_line_size << 2, + c->x86_clflush_size); + + /* Once we know this logic works, all the above code can be deleted. */ + if (c->x86_clflush_size > 0) { + pci_cache_line_size = c->x86_clflush_size >> 2; + printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n", + pci_cache_line_size << 2); + } else { + pci_cache_line_size = 32 >> 2; + printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n"); + } + pcibios_resource_survey(); if (pci_bf_sort >= pci_force_bf)
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