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SubjectRe: 2.6.32 regression (bisected): Video tearing/glitching with T400 laptops
On Mon, 12 Oct 2009 22:31:46 -0400
Theodore Tso <tytso@mit.edu> wrote:

> On Mon, Oct 12, 2009 at 12:05:10PM -0700, Jesse Barnes wrote:
> > On Mon, 12 Oct 2009 20:46:51 +0200
> > "Carlos R. Mafra" <crmafra2@gmail.com> wrote:
> >
> > > On Mon 12.Oct'09 at 9:54:38 -0700, Jesse Barnes wrote:
> > > > >
> > > > > Nope, unfortunately, it's not helping on my T400 laptop. I'm
> > > > > still getting huge amounts of glitching and tearing with this
> > > > > patch applied against -rc3.
> > > > >
> > > > > What I'm using for now to fix up my system is this patch.
> > > > >
> > > >
> > > > How about this one? I have one more idea to try out if this
> > > > doesn't work (hacking on it now).
> > >
> > > I was also experiencing something very similar to Theodore's bug
> > > report and, at least for me, the patch below fixed the issue (the
> > > previous one also had no effect).
> >
> > Cool, good to hear. Hopefully Ted and Keith will confirm too.
>
> Hmm, the amount of tearing seems to be a bit less frequent, but it's
> definitely still happening with this patch applied. Sorry....

Arg, I'm running out of ideas... How about this hack? I'll chat with
the chipset guys to see if we can figure out what's going on here...

--
Jesse Barnes, Intel Open Source Technology Center

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0466ddb..d5ec112 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -352,13 +352,24 @@

#define FBC_LL_SIZE (1536)

-/* Framebuffer compression for GM45+ */
+/*
+ * Framebuffer compression for GM45+
+ *
+ * GM45+ support tracking of a back buffer for use with page flipping.
+ * In this case, the "persistent" bit should be set and both nuke disable
+ * bits should be set as well. The back buffer is tracked by setting the
+ * HT fence bit in the chicken bit reg and pointing the CPU fence at the
+ * back buffer for tracking.
+ */
#define DPFC_CB_BASE 0x3200
#define DPFC_CONTROL 0x3208
#define DPFC_CTL_EN (1<<31)
#define DPFC_CTL_PLANEA (0<<30)
#define DPFC_CTL_PLANEB (1<<30)
#define DPFC_CTL_FENCE_EN (1<<29)
+#define DPFC_CTL_CSNUKE_DIS (1<<27)
+#define DPFC_CTL_MMIONUKE_DIS (1<<26)
+#define DPFC_CTL_PERSISTENT (1<<25)
#define DPFC_SR_EN (1<<10)
#define DPFC_CTL_LIMIT_1X (0<<6)
#define DPFC_CTL_LIMIT_2X (1<<6)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7a5fb79..ea808a9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2441,6 +2441,8 @@ static void g4x_update_wm(struct drm_device *dev, int unused, int unused2,
else
fw_blc_self &= ~FW_BLC_SELF_EN;
I915_WRITE(FW_BLC_SELF, fw_blc_self);
+ I915_WRITE(DSPFW1, (8 << 23) | (8 << 16) | (8 << 8) | (8 << 0));
+ I915_WRITE(DSPFW2, (1 << 31) | (8 << 28) | (8 << 8) | (8 << 0));
}

static void i965_update_wm(struct drm_device *dev, int unused, int unused2,

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