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SubjectRe: 2.6.29-rc libata sff 32bit PIO regression
Hello, I wrote:

>>>>>> > I've a Dell Precision 670 here (four-year-old EM64T Xeon with
>>>>>> ata_piix)
>>>>>> > which doesn't like your commit
>>>>>> 871af1210f13966ab911ed2166e4ab2ce775b99d
>>>>>> > libata: Add 32bit PIO support. Full dmesg (and .config)
>>>>>> attached, but
>>>>>> > here's an extract showing the start of the error messages on
>>>>>> ata2:
>>>>>>
>>>>> Cool - so we need two different 32bit PIO methods - at least
>>>>> according to
>>>>> the docs for the AMD we should use entirely 32bit I/O there. Fun fun
>>>>>
>>>> Could you refer me to the exact AMD doc that requires that?
>>>>
>>>
>>> AMD762 page 82, under DevB:1x40 bit 14 and bit 12
>>>
>>
>> What exactly AMD-762 document has this? I'm not seeing it in either
>> stasheet ot software/BIOS design guide. Besides, AMD-762 is a north
>> bridge and doesn't include IDE.
>
> Finally found it in the AMD-768 datasheet.
>
>>> "Note: only 32-bit writes to the data port are allowed when this bit is
>>> set."
>>>
>>
>> Now tell me who forces you to set that bit (I assume it's the write
>> buffer enable) for the ATAPI devices?
>
> Yes, it's the write buffer enable (about which I have written already).

IMHO, this is the same situation as with the prefetch -- you want to
avoid additional data read (write in this case) cycles to with an ATAPI
device, so you have to turn it off.

MBR, Sergei




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