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    SubjectRe: [RFC patch 0/4] TSC calibration improvements

    On Thu, 4 Sep 2008, Alan Cox wrote:
    > > (And yes, I do the latching - it's not reqlly required since I only depend
    > > on the MSB, and it actually makes for slightly lower precision, but it's
    > > the "safe" thing. And I figured out that the reason I thought that the
    > Good job you don't. Various Cyrix/Geode chipsets have as errata #2
    > "Counter latch command is non-operational in the 8254 timer"

    Yeah, I had some memory of latch issues. I wrote the thing originally
    without the latching, which is why the whole thing is designed to igore
    the low cycle count. I just decided that doing the latching shouldn't
    hurt that much, even if it ends up being just a 1us no-op.

    It does mean that on any normal hardware, the expected error is roughly
    3us over 2048 PIT ticks, which if I do the math right (nominal PIT
    frequency: 1193182 Hz) is just under 0.2%. Or put another way, ~1750 ppm.

    Not doing the latching should make the expected error go down to 2us.

    Of course, the 2048 PIT ticks is just a random choice. It could be any
    multiple of 256 ticks, so that error can be made smaller. Maybe it's worth
    spending 10ms on this, and get it down by a factor of five (at which point
    the error on the PIT frequency is probably in the same order of


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